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Cupertino, California - USD Full Time Posted: Thursday, 8 November 2018
 
 
Senior Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States

Hardware

+ Deep knowledge of System Verilog test-bench language and UVM

+ Impactful experience developing scalable and portable test-benches

+ Significant experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations

+ Deep knowledge with serial protocols such as PCIe or USB

+ Proven experience in mixed signal verification methodology for IPs such as PHYs, PLLs etc

+ In lieu of UVM knowledge, C/C++ expert level knowledge

+ Deep knowledge of one of the Scripting languages: Python, Perl, TCL

+ Strong knowledge of formal verification methodology

*Description*

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC/IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.

*Education & Experience*

Masters Degree with 7 years or Bachelors Degree with 10 years

*Additional Requirements*

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Cupertino, California, United States of America
IT
USD
Apple
Apple
JS761998315/566242095
11/8/2018 3:28:42 PM

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